Determining SRTISS Arms Data Abort: Zero Register vs. Stack Pointer
When an ARM CPU encounters a data abort, the System Register Trace Interrupt Status and Set Enable (SRTISS) register can be used to determine if the Zero Register (ZR) or the Stack Pointer (SP) was being accessed during the fault.
ARM CPU Spec
The ARM CPU provides two types of registers for storing data: the Zero Register (ZR) and the Stack Pointer (SP). The ZR is a 32-bit register with a constant value of zero, while the SP is a 32-bit register containing the address of the current top of stack.
Data Abort
A data abort occurs when a memory access violation takes place during an instruction fetch, data read, or data write operation. There are two types of data aborts: pre-fetch abort and translation abort.
SRTISS Register
The SRTISS register provides information about the state of memory-related interrupts on the ARM CPU. This register contains several bits, each representing a different type of memory-related interrupt, including the data abort. The SRTISS register can be accessed using the MRC instruction.
Determining the Register
When a data abort occurs, the SRTISS register can be used to determine if the ZR or the SP was being accessed during the fault. This can be done by checking the DAZ bit, which indicates if the ZR was being accessed, and the DSP bit, which indicates if the SP was being accessed.
Code Block
The following code block demonstrates how to check the DAZ and DSP bits of the SRTISS register:
MRC p15, 0, , c13, c0, 1 @ Read the SRTISS register
TST , #0x400000 @ Check the DAZ bit
IT NE @ If not equal to zero, branch
NEQ dataAbortZeroRegister @ Branch to code handling ZR fault
TST , #0x200000 @ Check the DSP bit
IT NE @ If not equal to zero, branch
NEQ dataAbortStackPointer @ Branch to code handling SP fault
- ARM CPUs use the Zero Register (ZR) and Stack Pointer (SP) for storing data.
- A data abort occurs due to memory access violations during instruction fetch, data read, or data write operations.
- The SRTISS register provides information about memory-related interrupts.
- The DAZ bit of the SRTISS register indicates if the ZR was being accessed, and the DSP bit indicates if the SP was being accessed during the fault.
References
- Arm Architecture Reference Manual, Armv7-A and Armv7-R edition (link)