Number of NUMA nodes and CPU core selection for low latency systems

Number of NUMA nodes and CPU core selection for low latency systems

In the world of low latency systems, understanding the number of NUMA (Non-Uniform Memory Access) nodes and selecting the right CPU cores can greatly impact performance. In this article, we will explore these concepts and provide guidance for entry-level users.

What are NUMA nodes?

NUMA stands for Non-Uniform Memory Access, which refers to a computer architecture where multiple processors or CPU cores are connected to different memory banks. Each CPU core has its own local memory, and accessing memory outside its local NUMA node introduces additional latency.

Modern servers typically have multiple NUMA nodes, each with its own set of CPU cores and memory. Understanding the number of NUMA nodes in your system is crucial for optimizing performance.

Impact of NUMA nodes on latency

When a process running on a CPU core accesses memory from its local NUMA node, the latency is minimal. However, if the process needs to access memory from a different NUMA node, the latency increases significantly.

This latency increase is due to the need for interconnects between NUMA nodes, which introduce delays in memory access. Therefore, minimizing cross-NUMA node memory access is essential for low latency systems.

Choosing the right CPU cores

When selecting CPU cores for low latency systems, it is important to consider the number of NUMA nodes in your system.

If your system has a single NUMA node, you can freely choose any CPU core for your application. However, if your system has multiple NUMA nodes, it is recommended to assign your application threads to CPU cores within the same NUMA node.

By doing so, you can ensure that your application threads have fast access to their local memory, minimizing latency. This can greatly improve the overall performance of your low latency system.

Conclusion

Understanding the number of NUMA nodes and selecting the right CPU cores are essential for optimizing performance in low latency systems. By minimizing cross-NUMA node memory access and assigning threads to CPU cores within the same NUMA node, you can significantly reduce latency and improve overall system performance.

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