PCIe Bus Enumeration without IO Map: A Beginner's Guide
PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard, which is used for connecting devices in a computer. It has replaced the older PCI (Peripheral Component Interconnect) bus due to its higher data transfer rates and lower power consumption. One of the key concepts in PCIe is memory-mapped I/O (MMIO) which is used instead of IO-mapped I/O.
PCIe Bus Enumeration
Bus enumeration is the process of assigning a unique address to each device on the PCIe bus. This is done by the host controller, which scans the bus for devices and assigns them a unique address. The host controller also assigns a configuration space to each device, which contains information about the device such as its vendor ID, device ID, and status registers. The configuration space can be accessed by the host controller to configure the device and by the device to report its status.
Memory-mapped I/O (MMIO)
Memory-mapped I/O (MMIO) is a technique used in PCIe to access the configuration space and I/O registers of a device. In MMIO, the configuration space and I/O registers of a device are mapped to a specific range of memory addresses. This allows the host controller and the device to access the configuration space and I/O registers using normal memory access instructions. This is different from IO-mapped I/O, where the I/O registers are accessed using special I/O instructions.
Advantages of MMIO
MMIO has several advantages over IO-mapped I/O. First, it allows the host controller and the device to use the same instructions to access the configuration space and I/O registers. This simplifies the design of the host controller and the device. Second, MMIO allows the host controller to access the configuration space and I/O registers of a device using DMA (Direct Memory Access). This allows the host controller to access the configuration space and I/O registers of a device without involving the CPU, which can improve performance. Third, MMIO allows the host controller to access the configuration space and I/O registers of a device using cache coherency protocols. This allows the host controller to access the configuration space and I/O registers of a device without having to flush the cache, which can improve performance.
PCIe Bus Enumeration without IO Map
In PCIe bus enumeration without IO map, the host controller assigns a unique address to each device on the PCIe bus, but it does not assign an IO map. Instead, the host controller maps the configuration space and I/O registers of a device to a specific range of memory addresses using MMIO. This allows the host controller and the device to access the configuration space and I/O registers using normal memory access instructions. This is different from traditional PCIe bus enumeration, where the host controller assigns an IO map to each device on the PCIe bus.
Example of PCIe Bus Enumeration without IO Map
#include
#include
// PCIe configuration space address
#define PCIE_CONFIG_SPACE_ADDR 0xC0000000
// PCIe device vendor ID
#define PCIE_DEV_VENDOR_ID 0x10DE
// PCIe device device ID
#define PCIE_DEV_DEVICE_ID 0x1380
int main() {
// Calculate the address of the device's configuration space
uint64_t config_space_addr = PCIE_CONFIG_SPACE_ADDR + (0x1000 * 0) + (0x10 * 0) + (0x100 * 0);
// Read the vendor ID from the configuration space
uint16_t vendor_id;
*(volatile uint16_t
*)&vendor\_id = *(volatile uint16\_t \*)config\_space\_addr;
if (vendor\_id == PCIE\_DEV\_VENDOR\_ID) { // Device found // Read the device ID from the configuration space uint16\_t device\_id;
\*(volatile uint16\_t \*)&device\_id = \* (volatile uint16\_t \*)(config\_space\_addr + 0x02);
if (device\_id == PCIE\_DEV\_DEVICE\_ID) { // Device found // Configure the device }
}
return 0;
}
PCIe bus enumeration without IO map is a technique used in PCIe to assign a unique address to each device on the PCIe bus and map the configuration space and I/O registers of a device to a specific range of memory addresses using MMIO. This allows the host controller and the device to access the configuration space and I/O registers using normal memory access instructions. This technique has several advantages over traditional PCIe bus enumeration, including simplified design, improved performance, and the ability to use DMA and cache coherency protocols.
References
- MindShare PCIe 3.0 Specification
- PCI-SIG PCI Express Base Specification Revision 3.0
- Intel 6 Series Chipset Family datasheet
This article is intended to provide a beginner's guide to PCIe bus enumeration without IO map. It covers key concepts such as bus enumeration, memory-mapped I/O, and the advantages of using PCIe bus enumeration without IO map. The article also includes an example of PCIe bus enumeration without IO map and a list of references for further reading.
Note: This article is not intended to be a complete guide to PCIe bus enumeration without IO map. It is intended to provide a basic understanding of the topic for beginners. For a more detailed understanding, please refer to the references provided.
End of article.